Field of Invention
The present invention relates to the field of semiconductor device and integrated circuit technologies, specifically to a semiconductor cell structure of a high-voltage and low-drift region on-resistance.
Description of Related Arts
Currently, for a semiconductor device, especially a high-voltage silicon power device, optimization design of a breakdown voltage and on-resistance of a drift region bearing a withstand voltage is mutually influential and contradictory. Generally, it is quite difficult to obtain low on-resistance while a high breakdown voltage is obtained. Certainly, a case in which a minority carrier or non-equilibrium dual carrier modulation exists in the drift region bearing a withstand voltage when a device is on is not included, for example, devices such as an IGBT (Insulated Gate Bipolar Transistor), a PIN (P-I-N diode), and a GTO (Gate Turn-Off Thyristor). Generally, in a high-voltage semiconductor silicon device of over 100 V, a large part of on-resistance is occupied by a high-voltage drift region of the device. This situation becomes more and more serious with the increase of an operating voltage. This is the most famous silicon theoretical limit of a non-modulated power device in which the 2.5th power of a breakdown voltage is proportional to drift region on-resistance.
In order to reduce drift region on-resistance of a non-modulated power device at a high voltage, for more than a decade, the industry has proposed some methods and device cell structures for reducing on-resistance while maintaining the breakdown voltage constant for a conventional device cell structure. The most famous device is a device of a super junction structure improved based on the RESURF two-dimensional electric field principle and the charge balance principle. Wherein, a VDMOS power device named CoolMOS™ from Infineon Technologies commercializes the structure. Such a device forms a PN junction approximately parallel to the flow direction of the current through epitaxy for more than three times and location impurity injection for corresponding times, and strictly requires the total quantities of impurities of the PN junction in a direction perpendicular to the current to be equal and achieve space depletion charge balance. Only in this way can the highest voltage be adequately borne, and can a voltage drop generated when a current flows through the drift region be reduced, and can the theoretical limit of an ordinary one-dimensional parallel-plane PN junction drift region on-resistance and the 2.5th power of a withstand voltage be better broken. However, such a process implementation has large difficulty and high costs.
In addition, there are many new implementation methods and equivalent structure technical solutions based on a super junction theory in the prior art. Solutions that can be industrially implemented in these technologies are mainly structures and methods characterized by a deep groove. Especially, oblique injection and epitaxial filling after the deep groove are relatively close to the super junction theory, and it is relatively easier to implement the oblique injection and epitaxial filling.
In general, all cores in the prior art are based on a two-dimensional theory of the super junction and are also consistent with the RESURF principle. The core demand is that if a two-dimensional semiconductor is to bear a voltage higher than that of a parallel-plane junction in a certain direction, and drift region on-resistance may be further reduced at the same time, a PN junction needs to be formed on a side surface of the semiconductor in a direction parallel to the current, and it is also required that the PN junction is fully depleted on both sides and can exactly reach a charge balance when the device bears the high voltage, while an impurity concentration or a space depletion layer charge satisfies the RESURF condition. In a rare case, a fixed and uniform charge in an insulator such as an oxide layer may be used to replace a space depletion layer charge that is at one side of the PN junction and that does not join in electric conduction.
Using FIG. 1 as an example to synthetically describe features in the prior art and problems or shortcomings of implementing the features. FIG. 1 is a highly-summarized schematic diagram of a high-voltage low-conduction cell structure in the prior art. As shown in the figure, a region 1 in the figure is a drift region bearing a high voltage when a device is turned off and is also a current channel when the device is turned on. A region 6 is an active region of the device, and may be a gate and channel region of a VDMOS, or may simply be a primary functional region such as a Schottky or high-voltage PN junction diode junction region of the device. A region 7 is a high-voltage and highly-doped region of the device, and may be a drain region of the VMDOS, or a highly-doped high-voltage electrode region with low resistance of a Schottky or PN junction diode.
It can be learned that, the active region in FIG. 1 (that is, the region 6), the drift region (that is, the region 1), and the high-voltage electrode region (that is, the region 7) form basic functional elements of such type of high-voltage power devices, and are a basic core structure that is of a high-voltage device based on an ordinary one-dimensional parallel-plane PN junction and that can independently operate. The drift region 1 is exactly a contradictory focus between a high voltage and a low on-resistance in such type of devices, because the drift region bears a high voltage in a reverse direction and becomes an inevitable way for a current during forward conduction.
In order to further improve device performance, that is, performance of a higher voltage and a lower on-resistance, the RESURF principle and a super junction charge balance two-dimensional effect mechanism are used. Existing technologies basically use a basic solution in which a region 2 whose impurity type of a current side is opposite to that of the drift region 1 is added in FIG. 1, and the so-called super junction is formed by the region 2 and the drift region 1 of the device. Such a solution is a first-generation high-voltage power semiconductor device that is based on the super junction theory and that breaks the theoretical limit of parallel-plane PN junction on-resistance and the 2.5th power of a withstand voltage. CoolMOS™ is a typical representative of such a structure and has been industrially implemented.
In addition, a few existing technical solutions further propose to use a charge in an insulating dielectric to equal or replace the region 2, for example, a charge 3 in the insulating dielectric in FIG. 1. In addition to the region 1, region 2, and region 3 in FIG. 1, some existing technical device cell structures further have some secondary additional structures, for example, region 4 and region 5 in FIG. 1, which are usually formed by a semi-insulating layer such as polycrystal and an oxide layer, and an insulating layer such as silicon nitride in an independent or combination manner. Mostly, the region 4 is formed by using a process technology of a deep groove as a feature, and the region 5 is generally deformation of some structures on a bottom portion of a deep groove 4. Usually, only the region 4 exists and the region 5 does not exist or is not required.
However, the existing technical solutions involved above have the following difficulties or shortcomings in the process implementation of the device structure:
1) For a technical solution in which a device cell structure does not have the region 4 and the region 5, it is difficult to control charge balance between the region 1 and the region 2. Generally, according to the RESURF principle, when silicon is at a voltage range of 100 V to 10000 V, a charge number surface density required by charge balance between the region 1 and the region 2 ranges from 1×1012 cm−2 to 2×1012 cm−2. A higher voltage indicates a stricter requirement. 10% change of the density is only from 1×1011 cm−2 to 2×1011 cm−2. For such charge control, persons having manufactured a semiconductor in this industry understand control difficulty of the range. Such a variation causes a super junction device of about 800 V to change by approximately 150 V. Therefore, a little conduction performance of an actual commercialized device usually needs to be sacrificed to balance a contradiction between breakdown and conduction characteristics, considering that the impact of a change of domain CD during a process also increases process implementation difficulty of a super junction device.
2) For a solution in which a device cell structure has the region 4 and region 5, similar to the case in which the region 4 and region 5 do not exist, it is still difficult to control charge balance between the region 1 and the region 2. In addition, when an insulating dielectric exists in the region 4 and (or) the region 5, an insulating dielectric layer interface charge or a fixed charge in an insulating dielectric is generally inevitably introduced into, and typically, for example, a fixed oxide charge in an oxide layer. There are relatively few fixed charges in a relatively thin oxide layer. For a thermal oxide layer of 20 nm or more, oxide charges in the thermal oxide layer generally range from 3×1010 cm−2 to 2×1011 cm−2. Certainly, when a process control level is relatively good, such charges are controllable and have great repeatability. Even so, for a high-voltage power device, an operating environment for the device is usually severe, and it is inevitable that the device is interfered by a spike voltage. This easily leads to charge injection or degradation of the oxide layer, and consequently, a super junction loses charge balance and stability of operation of the high-voltage device is affected.
3) For a rare case in which a charge in an insulating layer is used to replace the region 2 in FIG. 1 to form a super junction with the active functional region 1, on one hand, the impact of an uncertain charge peculiar to the foregoing general insulating layer still exists. On the other hand, an insulating layer charge currently used in the insulating layer generally uses metal cesium, belonging to alkali metals and being poorly compatible with a semiconductor silicon process.
4) In addition, in the prior art, there are currently two methods to implement a process solution that is relatively easy to implement and that uses a deep groove as a process feature, to be specific, large tilt angle ion implantation and a direct epitaxy method.
Wherein, the large tilt angle may use the high dose accuracy of ion implantation, but the accuracy of the tilt angle and the accuracy of equivalent impurity surface density ranging from 1×1010 cm−2 to 1×1011 cm−2 are pretty challenging. In addition, how to satisfy a requirement of a contemporary plane integration process and seal a deep groove without causing charge fluctuation in a super junction structure system is also a difficulty of process implementation. If the deep groove is sealed by using a dielectric layer, it is a difficult to control a charge in the dielectric insulating layer, and a redundant injected impurity charge at a bottom portion of the deep groove needs to be carefully processed. If polycrystalline or monocrystalline semiconductor epitaxy is used, a space depletion layer or a monocrystalline flaw needs to be well controlled, otherwise, it will cause severe reverse electric leakage.
In addition, for the direct epitaxy method, on one hand, a doping dose needs to be accurately controlled, and the accuracy needs to be definitely controlled within an impurity surface density from 1 cm−2 to 2×1011 cm−2. On the other hand, it is also a difficulty to perfectly seal the deep groove without generating a flaw when monocrystalline is epitaxially grown in the deep groove, otherwise, it will also cause severe reverse electric leakage.
In conclusion, how to provide a high-voltage silicon power device with both of withstand voltage and low on-resistance and how to make it easier to implement the device in a manufacturing process have become a problem urgent to be resolved by those skilled in the art.